A traditional printed circuit board comprises a supporting substrate and copper-foil circuit traces. These traces are usually formed by the chemical etching of a pattern defined onto a laminated copper surface. Sometimes both front and back sides of the substrate carry circuit traces. Two-sided, or double-sided designs usually are interconnected through vias (holes) that have copper deposited around the hole walls. A related technology exists known as Thick Film. Here the supporting substrate comprises flat, thin pieces of alumina (Al.sub.2 O.sub.3) on which the traces are printed with an ink containing metal, glass frit, and other additives. When fired at the correct temperatures the ink fuses to form conductive traces to which components can be soldered. An important feature to Thick Film technology is that conductive traces can be interconnected by printed inks having specific electrical resistivity after being heated in a kiln (firing).
"Build Up Technology" is a way of creating multi-layer circuitry with high precision and very fine lines. It is therefore, like the Molded Electronic Package, a way of making things smaller. By adding multiple layers of circuit traces you can achieve more functions per unit area than can be achieved with a single layer. By using very fine traces one can achieve even more density. Traditional imaging, and the imaging processes used in the Molded Electronic Package, is screen printing where lines as fine as 0.125 mm are difficult to achieve. Build Up Technology is a known photo process, and lines in the 0.050 to 0.075 mm range are possible.
Countless variations of printed circuit boards exist, and many variations of the Build Up Technology process also exist. One application of both the printed circuit board process, and the Polymer Thick Film process is the Molded Circuit board. Here the process of converting a laminated sheet of material into the proper circuit board dimensions and having all the necessary holes, slots, and shapes are replaced by molding these features into the board. Circuit traces are applied to a board either during or after the molding process. Different methods exist for adding the electrically conductive traces to a surface. This includes such the use of Polymer Thick Film inks, sputtering, and vacuum deposition. Another method for adding the electrically conductive traces is to use Build Up Technology.
In the past the molded board with Polymer Thick Film traces (baking of the Polymer Thick Film ink creates the conductive circuit traces) found limited acceptance for a number of reasons. Printed Polymer Thick Film conductive traces have more resistance than copper foil traces. Also, electronic devices cannot be soldered to most Polymer Thick Film traces. Those electronic devices that were attached to solderable Polymer Thick Film inks did not have good adhesion to the molded substrate after the soldering process. Some Polymer Thick Film conductive inks contain lead which causes environmental concerns and which limits the ability to recycle the materials. Additionally, the molded plastic that could withstand soldering temperatures without warping were the engineering grade materials which are higher quality performing materials. These are more expensive, however, and when used, the cost advantage of the molding process is often lost. Some simple applications of the Molded Board with Polymer Thick Film traces but without components in Pockets and designed to fit into a connector have been used commercially, but in general commercial production of this type product has been limited.
Printing conductive layers over circuit board traces that are connected to and grounded by a ground plane is a known way to achieve shielding of the traces covered. The circuit traces are first sealed in an insulating layer, and then overprinted with a conductive layer. With this traditional approach it is not possible to shield the components which are attached to the circuit traces, but only the traces themselves.
Lassen's U.S. Pat. No. 4,602,318 describes achieving high density electronic networks by depositing filaments onto a substrate and encapsulating the filaments to achieve dimensional stability. Filaments are conductive or made conductive by various means. Access to these conductive traces is produced with the use of a high -energy beam to cut through and expose the filaments. Lassen claims the use of epoxy resin sheets, and polyimide resin sheets to create his circuitry.
Parker's U.S. Pat. No. 4,912,844 describes using a heated punch to define grooves and holes in a substrate. The grooves are then filled with solder to create a circuit trace which connects electronic devices.
Beaman's U.S. Pat. No. 5,371,654 describes a three dimensional electronic package with a plurality of assemblies interconnected by aligning the assemblies so they are adjacent, and interconnected by some means such as an elastomeric material, but other than a Polymer Thick Film.
Capote's U.S. Pat. No. 5,376,403 describes ink formulations which can be used to form circuit traces, but Capote does not describe or claim uses for his ink.
Hiller's U.S. Pat. No. 5,420,755 places a component in a hole cut into standard circuit board material, but does not claim using molded pockets in circuit boards. The component is attached with a standard solder connection. Placement of the component is in a cut hole and the solder joint is not different from using any common commercial solder joint to connect the electronic devices.
McGinley's U.S. Pat. No. 5,599,595 and No. 5,688,146 describes how circuit traces can be added to molded plastic to achieve a printed connector assembly. McGinley uses current technology to attach printed Polymer Thick Film conductive traces to the top surface of the Polymer Thick Film traces. McGinley uses current Polymer Thick Film methods to print resistors on the circuitry of the connector.
Marrocco's U.S. Pat. No. 5,646,231, No. 5,646,232, and No. 5,654,392 describe the use of rigid rod polymers to form a plastic molded circuit board. No mention is made as to how this is done, nor are any claims made concerning molded pockets in the substrate or attachments of the electrical devices placed in the pockets.
Nakagawa's U.S. Pat. No. 4,801,489 and Iwasa and Marooka's U.S. Pat. Nos. 5,066,692 and 4,970,354 describe how printed conductive inks can be used to create shielding properties on printed circuit boards, however all of these patents are for shielding on printed circuit boards. In my invention there is no circuit board, but rather a molded substrate containing inserted components. Also, In my invention the entire package may be shielded, and not just the circuit traces. This is a significant advantage over printed shielding that shields only the traces.
Higgins' U.S. Pat. No. 5,639,989 describes how shielding of both circuit traces and components mounted on the substrate can be achieved. Higgins patent would require applying an insulating layer over both traces and components and then applying a conductive layer over the insulating layer which connects to a ground plane. This is awkward to achieve since the surface is not planar, and these layers must be applied by spraying, dipping, pad printing, or some other method for applying a uniform thin layer to an irregular surface. In my invention the circuitry and components form a planar surface, and the layers can be easily printed with screen printing, Build Up Technology Masking or any other common commercial printing process.
Gorczyca's U.S. Pat. No. 5,492,586 discloses a construction whereby a number of semiconductor chips or bare die can be interconnected in a planar structure. Unlike the present invention, the fixing and orientation of the die is achieved by a complex operation involving forming a large well and the "potting" the chips in situ. Also, interconnection does not employ the printing of Build Up Technology. In any case the Gorczyca device is still just another component; known as a Multi-Chip Module (MCM) albeit of complex function. The present invention enables the construction of a complete functioning system (not just a component) by placing a complete set of components both active and passive and including MCMs into precise molded pockets forming a planar structure. Gorczyka's invention is to replace the more common methods of wire bonding or "flip chipping" with plating or sputtering methods as a means of joining the semiconductor chips to the interconnection metallisation within the internal structure of the MCM. This is not relevant to the present invention since the internal structure of such a component is not a factor.
In Weber's U.S. Pat. No. 5,652,463 a transfer molded electronic package is disclosed. In Weber the novelty is that it uses passages under the heat sink to allow the molding compound in molten form to encapsulate the die and wire bonds. In the abstract Weber clearly states a pin grid array, i.e., components ready to be attached to the PCB. In Applicants invention no molten form of the molding compound is used to encapsulate the electronic device.
In Beaman's U.S. Pat. No. 5,371,654 there is a disclosure of a complicated structure for packaging electronic devices in a three dimensional structure of substantial complexity. Beaman clearly shows the need for the Applicant's invention which is a much simpler process to accomplish the same end goal of packaging electronic devices.
In Takagi's U.S. Pat. No. 4,800,459 there is disclosed an assembly which interconnects a number of components. However Takagi is ceramic and laminated and not thermoplastic and molded. The high temperature nature of Takagai precludes the use of Build Up Technology and any semiconductors. This, in effect, Takagai must be regarded as a composite or integrated component, in this case an assembly of passive devices similar to Gorczyca's assembly of active devices. Clearly, the Applicant's structure is different and more useful.